//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
//Date        : Mon Nov 11 21:00:59 2019
//Host        : DESKTOP-EVCEGS1 running 64-bit major release  (build 9200)
//Command     : generate_target Complement_5bit_wrapper.bd
//Design      : Complement_5bit_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module Complement_5bit_wrapper
   (A0,
    A1,
    A2,
    A3,
    PM,
    Y0,
    Y1,
    Y2,
    Y3,
    Y4);
  input A0;
  input A1;
  input A2;
  input A3;
  input PM;
  output Y0;
  output Y1;
  output Y2;
  output Y3;
  output Y4;

  wire A0;
  wire A1;
  wire A2;
  wire A3;
  wire PM;
  wire Y0;
  wire Y1;
  wire Y2;
  wire Y3;
  wire Y4;

  Complement_5bit Complement_5bit_i
       (.A0(A0),
        .A1(A1),
        .A2(A2),
        .A3(A3),
        .PM(PM),
        .Y0(Y0),
        .Y1(Y1),
        .Y2(Y2),
        .Y3(Y3),
        .Y4(Y4));
endmodule
